Conventional silicon-on-insulator (SOI) CMOS devices typically have a thin layer of silicon, also known as the active layer, on an insulator layer such as a buried oxide (BOX) layer. Active devices, such as MOS transistors (MOSFETs), are formed in active regions within the active layer. The size and placement of the active regions are defined by isolation regions, such as shallow trench isolation (STI) regions. Active devices in the active regions are isolated from the substrate by the BOX layer.
Devices formed on SOI substrates exhibit many improved performance characteristics over their bulk substrate counterparts. SOI substrates are particularly useful in reducing problems relating to reverse body effects, device latch-up, soft-error rates, and junction capacitance. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.
Conventional CMOS technology typically includes fabricating NMOS and PMOS devices on active regions consisting of a semiconductor layer having a single crystal orientation. This, however, is not the optimum CMOS configuration because electrons have their greatest mobility in the {100} family of planes, while holes have their greatest mobility in the {110} family of planes. Consequently, one type of device is frequently fabricated with the optimum crystal orientation, while the other type of device functions with less than optimal carrier mobility.
Workers have recognized these problems and have developed techniques for fabricating CMOS devices on SOI hybrid substrates. Such substrates have multiple crystal orientations that are independently optimized for NMOS and PMOS devices. For example, U.S. Pat. No. 5,384,473 to Yoshikawa et al. describes a method for fabricating PFETs on (110) surfaces and NFETs on (100) surfaces through wafer bonding and selective epitaxy. U.S. Pat. No. 6,107,125 to Jaso et al. describes overcoming floating body effects in SOI substrates. U.S. Pat. No. 4,889,829 to Kawai describes the formation of transistors in SOI substrates. U.S. Pat. No. 4,857,986 to Kinugawa, describes some of the effects of crystal orientation on carrier mobility.
Many problems encountered in CMOS fabrication involve forming isolation regions between different polarity devices. For example, some conventional CMOS hybrid orientation methods include fabricating isolation regions, e.g., shallow trench isolation (STI) regions, before the step of forming an epitaxial silicon layer. This particular fabrication sequence leads to problems. The differential etch rates among various isolation and semiconductor materials complicates manufacturing of hybrid orientation CMOS devices. Accordingly, conventional CMOS manufacturing methods that include forming STI regions after SOI epitaxy suffer yield losses from etching of isolation regions.
What are needed then are more robust manufacturing methods and device structures to more effectively integrate CMOS isolation structures and SOI hybrid orientation technology.